Receiver having clock recovery unit based on delay locked loop

ABSTRACT

A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a receiver of a display driving system, and more particularly, to a receiver having a clock recovery unit based on a delay locked loop, wherein a PLL (phase locked loop) structure is excluded and a clock recovery unit realized using only a DLL (delay locked loop) structure without using a separate oscillator for generating a reference clock signal is employed so that a clock signal embedded between data signals to the same level can be recovered.

2. Description of the Related Art

In general, display devices include a timing controller which processes image data and generates a timing control signal so as to drive a panel for displaying the image data, and data drivers which drive the panel using the image data and the timing control signal transmitted from the timing controller.

Interfaces for transmitting image data to be displayed, between the timing controller and the data driver, include a multi-drop signaling interface, in which the data drivers share a data signal line and a clock signal line, a PPDS (point-to-point differential signaling) interface, in which data differential signals and clock differential signals are separately supplied to the respective data drivers, and an interface, in which data and clock signals are separated into multiple levels and data differential signals with the clock signals embedded therein are transmitted from the timing controller through independent signal lines to the data drivers.

The present applicant has proposed an interface in Korean Patent Application No. 10-2008-0102492, in which a single level signal with a clock signal embedded between data signals (LVDS data) to the same level is used and data and a clock signal are transmitted together by an independent single signal line so that the data and the clock signal can be recovered by a receiver.

In the interface for transmitting data differential signals with clock signals embedded therein to the data drivers by respective independent signal lines, a transmitter generates a transmission signal that corresponds to respective data bits and transits periodically. The periodic transition can occur by dummy bits that are inserted between data bits of a predetermined number. That is to say, the periodic transition occurs due to the fact that a portion immediately before and after the data bits to be transmitted has a value different from the data bits. In this case, since a receiver provided in the data driver cannot receive a separate clock signal, in order to receive the data differential signals with the embedded clock signals and recover original data, the clock signals embedded between the data signals should be recovered from the received differential signals.

Therefore, the receiver should be provided with a recovery circuit for recovering the clock signals, and it is the norm in the conventional art that such a clock recovery circuit is configured to have a phase locked loop (PLL) structure. That is to say, because a reference clock signal as a clock signal generated by oscillation inside the receiver is needed to recover the received data, it is the norm that the clock signal recovery unit is configured by the phase locked loop (PLL) which has an oscillator for generating the reference clock signal.

As is disclosed in Korean Patent No. 868299, a conventional receiver provided in the data driver includes a clock generation unit which is configured to generate a received clock signal from the periodic transition of a differential signal received through a signal line, and a sampler which is configured to sample the differential signal according to the received clock signal and recover data bits.

The clock generation unit includes a transition detecting circuit configured to output a signal corresponding to a time difference between the periodic transition of the received differential signal and the transition of a feedback clock signal, and an oscillator configured to change the phases of the feedback clock signal and the received clock signal in response to the signal outputted from the transition detecting circuit.

The transition detecting circuit is configured in such a manner that the oscillation frequency of the oscillator is determined by the clock signal inputted upon initial synchronization and the operation of a transition detector is interrupted or restarted in response to an enable signal when data is inputted thereafter. In this case, while the enable signal is generated by the clock signal inputted upon the initial synchronization, since there is no clock edge during a time interval excluding the interval of the enable signal, no influence is exerted on the generation of the received clock signal.

Therefore, the clock generation unit is configured in such a manner that only the rising edge or the falling edge of the received signal composed of the dummy bits is recognized as a transition during an interval in which the enable signal has a high logic level and is not recognized as a transition during an interval in which the enable signal has a low logic level, so that the frequency and the phase of the received clock signal generated by the oscillator deviate from the periodic transition by the dummy bits.

Thus, the conventional clock generation unit is configured based on the phase locked loop (PLL) structure having a characteristic that the feedback signal in the oscillator is inputted again to the oscillator after the initial synchronization to generate the enable signal.

However, the conventional clock generation unit configured based on the phase locked loop (PLL) structure has a problem in that jitter continuously accumulates in the phase lock loop (PLL) as an internal feedback loop.

Also, the conventional clock generation unit may be configured to have not only the characteristic of a delay locked loop (DLL) in that the received signal is directly inputted to the oscillator in the initial synchronization to generate the enable signal but also the characteristic of the phase locked loop (PLL) in that the feedback signal in the oscillator is inputted to the oscillator after the initial synchronization to generate the enable signal.

Nevertheless, the conventional clock generation unit, which is configured to operate by the delay locked loop (DLL) structure in the initial synchronization and by the phase lock loop (PLL) structure after the initial synchronization, has a problem in that the oscillation frequency and the phase are likely to be distorted due to the change of the loop during operation.

Further, since the enable signal is generated by the phase locked loop (PLL) structure after the initial synchronization, a problem is still caused in that jitter continuously accumulates in the phase locked loop (PLL) as an internal feedback loop.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and an object of the present invention is to provide a receiver having a clock recovery unit based on a delay locked loop, wherein a PLL (phase locked loop) structure in which an input signal (a clock-embedded data (CED) signal) received through a signal line is not inputted to a VCO (voltage-controlled oscillator) and is compared, in terms of phase, with a reference clock signal as an internal clock signal generated by a separate internal oscillator and the phase of the internal clock signal is adjusted to be used for the recovery of data, is excluded, and only a delay locked loop is employed to recover a clock signal in such a manner that an input signal (a clock-embedded data (CED) signal) is directly inputted to a delay line (VCDL) and is delayed and a reference clock signal is generated without using a separate internal oscillator to be used for the recovery of data, thereby preventing jitter from accumulating in a receiver which does not separately use a clock signal, due to continuous transmission of the clock signal through a feedback loop.

In order to achieve the above object, according to one aspect of the present invention, there is provided a receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, including a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal, wherein the input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level, and wherein the clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.

According to another aspect of the present invention, the clock recovery unit is configured to generate a reference clock signal using a master clock signal recovered by the input signal (the CED signal) inputted to a delay line during a clock training interval, and to generate a reference clock signal using a master clock signal recovered by the data signals having the clock signal embedded therebetween after the clock training interval ends.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects, and other features and advantages of the present invention will become more apparent after a reading of the following detailed description taken in conjunction with the drawings, in which:

FIG. 1 is a block diagram illustrating a receiver for receiving a single level signal with an embedded clock signal in accordance with an embodiment of the present invention;

FIG. 2 is of exemplary views showing transmission data composed of single level signals with embedded clock signals in accordance with the embodiment of the present invention;

FIG. 3 is a configurational view of a clock recovery unit in accordance with the embodiment of the present invention;

FIG. 4 is a configurational view of a clock generator in accordance with the embodiment of the present invention; and

FIGS. 5 and 6 are timing diagrams illustrating operations of the clock recovery unit in accordance with the embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

Reference will now be made in greater detail to a preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a block diagram illustrating a receiver for receiving a single level signal with an embedded clock signal in accordance with an embodiment of the present invention.

Referring to FIG. 1, a receiver for receiving a single level signal embedded with a clock signal includes a serial-to-parallel converter 100 configured to receive a single level signal (clock embedded data: CED) transmitted through a serial signal line from a timing controller, convert the single level signal into parallel data and transmit recovered data to a display panel, and a clock recovery unit 200 configured to extract a clock signal embedded in the single level signal (CED signal), transmit to the serial-to-parallel converter 100 a sampling clock signal to be used for the recovery of the data signal and recover a received clock signal to be used for the output of data, as a recovered clock signal.

In the present invention, in order to solve the problems caused in a clock recovery unit configured based on a phase locked loop (PLL) due to the fact that jitter continuously accumulates as a clock signal generated in the clock recovery unit passes through an internal feedback loop, the clock recovery unit 200 is configured only using a delay locked loop (DLL) in which jitter does not continuously accumulate, so that a clock signal can be recovered by the receiver without using an oscillator for generating a separate reference clock signal. In this regard, since the other component parts of the receiver, such as the serial-to-parallel converter 100, excluding the clock recovery unit 200 can be configured similarly to a conventional receiver for receiving a single level signal and implementing recovery, the configuration of the clock recovery unit 200 which is formed based only on the delay locked loop (DLL) will be described below in detail.

The single level signal (CED signal) to be received by the receiver is a signal in which a clock signal is embedded between data signals to be transmitted, and is transmitted from the timing controller through the signal line to a data driver. At this time, while it is preferred that the single level signal (CED signal) have the clock signal embedded at the same level between the data signals, it is to be understood that the clock signal can be embedded at multiple levels. The CED signal as an input signal received by the receiver through the signal line may comprise one differential signal or a single-ended signal.

FIG. 2 is of exemplary views showing transmission data composed of single level signals with embedded clock signals in accordance with the embodiment of the present invention.

Referring to FIG. 2, the transmission data (the CED signal) comprising the single level signal is constructed by periodically inserting clock bits of the same level between data bits and inserting a dummy bit between data and clock bits to so as to represent the rising edge or the falling edge of the inserted clock bits. At this time, it is of course possible to increase the width of the dummy bit and the clock bits so as to ease circuit design.

The timing controller transmits transmission data (the CED signal) comprising only the clock signal before transmitting data, thereby starting clock training. The data driver recovers the received clock signal to be used for data sampling, in response to the CED signal transmitted during a clock training interval after the combination of a LOCK signal of the delay locked loop DLL itself and a LOCK signal inputted from another adjacent data driver or a control signal informing the ending of initial synchronization becomes an “H” state (a high logic state), and outputs LOCK signals LOCK₁˜LOCK_(N) to an “H” state when the received clock signal is stabilized.

The timing controller ends the clock training after the lapse of a predetermined time and starts the transmission of the CED signal. If the LOCK signal changes to an “L” state (a low logic state) during the transmission of the data, the timing controller immediately restarts the clock training and maintains the clock training for a preset time.

FIG. 3 is a configurational view of a clock recovery unit in accordance with the embodiment of the present invention.

Referring to FIG. 3, the clock recovery unit 200 includes a clock generator 210 configured based only on the delay locked loop (DLL) to generate a master clock signal MCLK from the input signal (CED signal), such that the clock signal can be recovered from the single level signal (CED signal) as data transmitted from a transmitter, and at least one sampling clock signal and the received clock signal to be used for the detection of data can be generated; a delay line 220 configured to delay the master clock signal MCLK generated in the clock generator 210 and output received clock signals recovered as recovered clock signals to have various phases depending upon delay amounts; a phase difference detector 230 configured to compare the received clock signals from the delay line and detect phase differences or time differences; and a low pass filter 240 configured to generate a delay controlled signal VCTRL depending upon a comparison result from the phase difference detector 230 and supply the delayed signal to the delay line 220.

The clock generator 210 is configured to generate a mask signal MASK, a pull-up signal PU or a pull-down signal PD in response to at least one signal among various delayed clock signals outputted from the delay line 220 and recover the clock signal embedded between the data signals. Therefore, the clock generator receives as an input the delayed clock signals CK₁, CK₂ . . . CK_(2N+1) outputted from the delay line 220, and generates the master clock signal MCLK by the signal (the CED signal) inputted during the clock training interval before the delayed clock signals CK₁, CK₂ . . . CK_(2N+1) are generated. At this time, the number of the delayed clock signals should be at least equal to or greater than 2N+1, where N is a natural number that indicates the number of data bits existing between clock bits.

FIG. 4 is a configurational view of a clock generator in accordance with the embodiment of the present invention.

Referring to FIG. 4, the clock generator 210 includes a mask signal generator 211 configured to receive the delayed clock signals and generate a mask signal MASK; a pass switch 212 configured to switch a cutoff switch in response to the mask signal MASK and control the transmitting state of the input signal (the CED signal); a cutoff switch configured to control direct transmission of the input signal (the CED signal) in response to the LOCK signal transmitted from the timing controller and the mask signal MASK; a pull-up section 214 and a pull-down section 215 configured to complementarily operate with respect to each other in response to at least one signal of the delayed clock signals CK₁, CK₂ . . . CK_(2N+1) when the cutoff switch is turned off and generate and output the master clock signal MCLK; and a first switch 216 configured to connect one end of the pull-up section 214 to a power supply voltage VDD and a second switch 217 configured to connect one end of the pull-down section 215 to a ground voltage GND. At this time, the LOCK signal is a signal that informs the ending of the initial synchronization, and indicates that the operation of the delay locked loop is stabilized or an external input signal is stabilized.

The mask signal generator 211 comprises a masking circuit which receives the delayed clock signals CK₁, CK₂ . . . CK_(2N+1)) outputted after being delayed through a plurality of inverters in the delay line 220 so as to recover received clock signals and detects the rising edges or the falling edges of the clock signals.

The pass switch 212 is switched in response to the LOCK signal and controls the operation of the cutoff switch 213 so that the mask signal MASK for detecting the edges of the clock signals can be transmitted. The pass switch 212 has one end which is connected to the mask signal generator 211 and the other end which is connected to the cutoff switch 213 for cutting off the transmission of the input signal (the CED signal) as the output of the clock generator 210.

At this time, the pass switch 212 is configured in such a manner that the mask signal MASK is connected to the cutoff switch 213 in response to the LOCK signal or the logic value of “1”, that is, a value indicating a logic high state is connected to the cutoff switch 213. In other words, in the case where the LOCK signal is in a logic high state, the cutoff switch 213 operates by the mask signal MASK, and in the case where the LOCK signal is in a logic low state, the input signal (the CED signal) is directly connected to the master clock signal MCLK.

Also, the cutoff switch 213 has one end which is connected to a signal line connected to the receiver and the other end which is connected to the delay line 220. The cutoff switch 213 is configured to control the direct transmission of the input signal (the CED signal) as the master clock signal MCLK to the delay line 220 and receive the mask signal MASK for detecting edges, from the pass switch 212.

The other end of the cutoff switch 213 is connected as well to the connection node of the pull-up section 214 and the pull-down section 215 which is connected to the delay line 220, and cuts off the output of the input signal (the CED signal) and outputs the signal recovered by pull-up or pull-down operation.

Hence, the cutoff switch 213 is configured to operate by the mask signal MASK transmitted from the pass switch 212 and be controlled to detect the rising edge or the falling edge of the input signal (the CED signal) when the LOCK signal is in a logic high state, and operate by the logic value “1” and allow the input signal (the CED signal) to be directly transmitted to the master clock signal MCLK when the LOCK signal is in a logic low state.

Since the state in which the LOCK signal is in the logic low (L) state corresponds to the clock training interval, the pass switch 212 is connected to the logic value of “1”, and the cutoff switch 213 transmits the input signal (the CED signal) as the master clock signal MCLK irrespective of the logic state of the mask signal MASK. Thus, the clock signal transmitted from the clock generator 210 during the clock training interval is transferred to the delay line 220.

Namely, while an initial signal having a period corresponding to the period of the clock signal inserted between the data signals when the timing controller transmits the signal is needed to recover the edges of the clock signal, the initial signal can be obtained, without using a separate oscillator for generating a reference clock signal, by outputting, as it is, the input signal transmitted during the clock training interval, from the clock generator 210, transferring the input signal to the delay line 220 comprising a voltage-controlled delay line (VCDL) or a current-controlled delay line (CCDL), and then delaying the input signal.

However, in the case where the LOCK signal is in a logic high (H) state, the transmission of the input signal (the CED signal) is controlled by the mask signal MASK which is generated by the mask signal generator 211, the rising edge or the falling edge is detected. That is to say, during the interval in which the mask signal MASK is in the logic high (H) state, the clock edge of the input signal (the CED signal) is transferred as an output, and during the interval in which the mask signal MASK in the logic low (L) state, the cutoff switch 213 is operated to prevent the input signal (the CED signal) from being transferred as it is, and the remaining portion of the input signal (the CED signal) excluding the edge of the clock signal is recovered through the operation of the pull-up section 214 or the pull-down section 215 using at least one delayed clock signal.

The pull-up section 214 and the pull-down section 215 generate the pull-up signal PU or the pull-down signal PD by using or combining at least one signal of the delayed clock signals CK₁, CK₂ . . . CK_(2N+1) when the LOCK signal is in the logic high state and the mask signal MASK is in the logic low state, thereby implementing the pull-up and pull-down operations and recovering the remaining portion of the input signal excluding the edge of the clock signal.

The pull-up section 214 is connected at one end thereof to the power supply voltage VDD through the first switch 216, and the pull-down section 215 is connected to the ground voltage GND through the second switch 217. The first switch 216 and the second switch 217 are controlled by the LOCK signal such that they are turned off when the LOCK signal is in the logic low (L) state and are turned on when the LOCK signal is in the logic high (H) state.

Accordingly, when the LOCK signal is in the logic low state, the first switch 216 prevents the pull-up section 214 from being connected to the power supply voltage VDD and the second switch 217 prevents the pull-down section 215 from being connected to the ground voltage GND. Also, when the LOCK signal is in the logic high state, the first switch 216 connects the pull-up section 214 to the power supply voltage VDD, and the second switch 217 connects the pull-down section 215 to the ground voltage GND.

In this way, due to the fact that the operations of the first switch 216 and the second switch 217 are controlled by the LOCK signal, when the LOCK signal of the delay locked loop (DLL) is in the logic low (L) state, it is possible to prevent the master clock signal MCLK from being erroneously generated due to the mis-operation of the pull-up section 214 and the pull-down section 215.

Hence, the pull-down signal PD outputs as an output the voltage value of the ground voltage GND when an input corresponds to a logic low output since the pull-up section 214 is turned off and a path is not formed between the power supply voltage VDD and the ground voltage GND, and the pull-up signal PU outputs as an output the voltage value of the power supply voltage VDD when an input combination corresponds to a logic high output since the potential of the output node thereof is raised to the power supply voltage, the pull-down section 215 is turned off and a path is not formed from the power supply voltage VDD to the ground voltage GND. A value determined by the switching operations of the pull-up section 214 and the pull-down section 215 is outputted as the master clock signal MCLK and is transferred to the delay line 220.

The delay line 220 may comprise a voltage-controlled delay line (VCDL) or a current-controlled delay line (CCDL). The delay line 220 is configured based on the delay locked loop (DLL) in such a manner that they do not have a feedback loop by which the delayed clock signals outputted are inputted again, and have a plurality of delay means capable of receiving, delaying and then outputting the master clock signal MCLK outputted from the clock generator 210.

Hereafter, the delay line will be stated as, but not limited to, the voltage-controlled delay line 220. Also, while it is illustrated in FIG. 3 that the delay means comprise inverters, it is to be noted that the delay means are not limited to the inverters but may comprise other delay cells or delay elements.

The voltage-controlled delay line 220 can generate a reference clock signal without using an internal oscillator, by delaying the master clock signal MCLK outputted from the clock generator 210 during the clock training interval, generating the delayed clock signals, and then comparing the phases of the master clock signal MCLK and two signals among the delayed clock signals of which time difference is the same as the period at which the clock bits are inserted. Further, after the clock training period ends, the received clock signal is generated by receiving and delaying the signal obtained by recovering the remaining portion excluding the edges of the clock signal included in the input signal (the CED signal) through the operations of the pull-up section and the pull-down section using the master clock signal MCLK.

The plurality of inverters provided to the voltage-controlled delay line 220 have a delay unit that is composed of a pair of inverters, and generate and output the delayed clock signals CK1, CK2, CK3, . . . CK_(2N+1) through pairs of inverters.

At this time, as the delayed clock signals outputted from the voltage-controlled delay line 220 are transmitted to the clock generator 210, the remaining portion of the clock signal excluding the portion inserted between the data can be recovered. That is to say, the delayed clock signal comprises a clock signal that is delayed while passing through the pair of inverters, and the output of the delayed clock signal is inputted to the clock generator 210, such that, when the LOCK signal is in the logic high state and the mask signal MASK is in the logic low state, the remaining portion of the clock signal excluding the edge of the clock signal can be recovered through the operation of the pull-up section 214 or the pull-down section 215.

Optional two clock signals among the input signal to the voltage-controlled delay line 220 and the clock signals delayed by the voltage-controlled delay line 220 are transmitted to the phase difference detector 230 such that the delay amounts of the clock signals delayed while passing through the inverters can be compared and a voltage control signal VCTRL capable of changing the delay amounts can be received from the low pass filter 240.

The phase difference detector 230 has as its inputs optional two clock signals among the input clock signal of the delay locked loop (DLL) and the clock signals delayed by the voltage-controlled delay line (VCDL) or the current-controlled delay line (CCDL) based on the delay locked loop, and is configured to generate the up/down signal UP/DN as a delay amount control signal corresponding to the time difference between the two clock signals and output the up/down signal UP/DN to the low pass filter 240.

At this time, when the LOCK signal is in the logic high state and the delay locked loop (DLL) is locked, the phase difference detector 230 has, as its inputs being comparison targets, two optional signals among the master clock signal MCLK outputted from the clock generator 210 and the delayed clock signals CK₁, CK₂, CK₃, . . . , CK_(2N+1) of which time difference is the same as the period at which the clock bits are inserted. While it is illustrated in FIG. 4 that the phase difference detector 230 has as its two inputs a first delayed clock signal CK₁ delayed first and a 2N+1^(st) delayed clock signal CK_(2N+1) delayed while passing through all of the plurality of pairs of inverters provided in the voltage-controlled delay line and is configured to generate the up/down signals depending upon the time difference between these two input clock signals, it is to be appreciated that the two delayed clock signals selected as the inputs to the phase difference detector 230 are not limited to these two clock signals.

Namely, when the time difference between the first delayed clock signal CK₁ and the 2N+1^(st) delayed clock signal CK_(2N+1) corresponds to the up signal UP as a positive signal, a charge pump 240 as the low pass filter charges electric charges, and when the time difference corresponds to the down signal DN as a negative signal, the charge pump 240 as the low pass filter discharges electric charges, so that the delay amount in the delay line 220 can be controlled.

The low pass filter 240 supplies a signal capable of adjusting a delay amount of the delay line by removing or reducing the high frequency component of the up/down signal UP/DN. While it is illustrated in the embodiment that the low pass filter 240 comprises the charge pump, it is to be appreciated that the low pass filter 240 is not limited to such and may comprise various loop filters.

In FIG. 3, in order for the charge pump 240 to receive the up/down signal UP/DN and output the voltage control signal VCTRL for adjusting the delay amount of the voltage-controlled delay line (VCDL) 220, the output terminal of the charge pump 240 is connected to the inverters provided to the voltage-controlled delay line 220. Accordingly, the charge pump 240 removes or reduces the high frequency component of the up/down signal generated by the time difference between the two clock signals in the phase difference detector 230, and outputs the voltage control signal VCTRL.

FIG. 5 is a timing diagram illustrating the operation of the clock recovery unit in accordance with the embodiment of the present invention.

Referring to FIG. 5, in order to recover the rising edge or falling edge of the clock signal inserted between the data, an input signal (a CED signal) that has a period corresponding to the period of the externally inserted clock signal when initially recovering the received clock signal is needed. Therefore, during the clock training interval in which the LOCK signal is in a logic low state, the input signal transmitted from the transmitter is outputted as it is as the master clock signal MCLK from the clock generator 210, and is transferred to the voltage-controlled delay line (VCDL) 220. During the clock training interval, the LOCK signal of the delay locked loop DLL is changed from the logic low (L) state to the logic high (H) state. Even though a separate oscillator is not provided, a reference clock signal to be used for the recovery of the clock signal can be generated by the master clock signal MCLK recovered during the clock training interval.

In order to recover the received clock signal using the delayed clock signal as at least one delay line output delayed by the delay line 220, the mask signal MASK for detecting the rising edge or the falling edge of the input signal (CED signal), and the pull-up signal PU and the pull-down signal PD for driving the pull-up section 214 and the pull-down section 215 to recover the remaining portion of the clock signal excluding the portion detected by the mask signal MASK are generated.

As shown in FIG. 5, if the delayed clock signal is delayed little by little by an amount delayed in the respective delay means and the transition timings of the first delayed clock signal CK₁ and the 2N+1^(st) delayed clock signal CK_(2N+1) correspond to each other, the up/down signal is not needed and a current state can be maintained. However, if the transition timings of the two signals do not correspond to each other and a phase difference occurs between the two signals, a delay amount is adjusted by the voltage control signal VCTRL that is generated through charge and discharge in the loss pass filter 240.

Moreover, only when both the LOCK signal and the mask signal MASK generated in the mask signal generator are in the logic high state, the clock edge of the input signal (the CED signal) is detected, and if the mask signal MASK is in the logic low state, the remaining portion of the clock signal excluding the edges is recovered by the pull-up signal PU and the pull-down signal PD for operating the pull-up section 214 and the pull-down section 215.

Hence, it is possible to generate the received clock signal as the recovered clock signal that is obtained by recovering the clock signal embedded in the input signal (the CED signal) to the same level while preventing jitter from accumulating through nonuse of a separate phase fixed loop and not using a separate internal oscillator.

FIG. 6 is a timing diagram illustrating another operation of the clock recovery unit in accordance with the embodiment of the present invention.

Referring to FIG. 6, in order to recover the clock signal embedded in the input signal (the CED signal) as described above, the mask signal MASK for detecting the rising edge or falling edge of the input signal (CED signal) using at least one delayed clock signal generated through delaying and outputting the input signal (the CED signal) during the clock training interval by the delay line 220, and the pull-up signal PU and the pull-down signal PD for recovering the remaining portion of the clock signal excluding the portion detected by the mask signal MASK are generated.

The input signal (the CED signal) shown in FIG. 6 is illustrated having a dummy bits preceding the clock signal. When both the LOCK signal and the mask signal MASK are in the logic high state, the transition of the clock signal embedded after the dummy bit is perceived, and the rising edge or falling edge is detected. At this time, depending upon whether the rising edge or the falling edge of the input signal (the CED signal) is detected, the sequence of the pull-up signal PU and the pull-down signal PD for driving the pull-up section 214 and the pull-down section 215 can be changed.

In these ways, in the present invention, the receiver generates the initial clock signal to be used in the receiver, using the input signal (the CED signal) transmitted during the clock training interval, detects the edge of the clock signal embedded between data signals to the same level, by the initial clock signal, recovers the remaining portion of the clock signal excluding the portion detected in this manner, and generates the received clock signal as the recovered clock signal. As a consequence, the clock signal can be recovered from the output signal of the voltage-controlled delay line 220 based on the delay locked loop (DLL) without using the phase locked loop (PLL) for generating the internally oscillating clock signal.

As is apparent from the above description, the present invention provides advantages in that, since a clock recovery unit configured based only on a delay locked loop (DLL) is employed to recover a clock signal transmitted while being embedded between data signals to the same level, it is possible to prevent jitter from accumulating owing to a feedback loop in a phase locked loop and disturbance from occurring in an oscillating frequency and a phase due to mixed use of a delay locked loop and a phase locked loop.

Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the invention as disclosed in the accompanying claims. 

1. A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, including a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal, wherein the input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level, and wherein the clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.
 2. The receiver according to claim 1, wherein the clock recovery unit is configured to generate a reference clock signal using a master clock signal recovered by the input signal (the CED signal) inputted to a delay line during a clock training interval, and to generate a reference clock signal using a master clock signal recovered by the data signals having the clock signal embedded therebetween after the clock training interval ends.
 3. The receiver according to claim 2, wherein the clock recovery unit comprises: a clock generator configured to control output of the input signal (the CED signal) and delayed clock signals and output values thereof, and generate the master clock signal; a delay line having a plurality of delay means for delaying the master clock signal, and configured to output the delayed clock signals recovered to have various phases depending upon delay amounts; a phase difference detector configured to compare the master clock signal and the delayed clock signals, detect time differences or phase differences between the signals, and generate an up/down signal for controlling the delay amounts of the delay line; and a low pass filter configured to remove or reduce a high frequency component of the up/down signal generated in response to a comparison result in the phase difference detector, and adjust the delay amounts of the delay line.
 4. The receiver according to claim 3, wherein the clock generator comprises: a mask signal generator configured to receive the delayed clock signals, and generate a mask signal for detecting a rising edge or a falling edge of the clock signal embedded in the input signal (the CED signal); a pass switch configured to apply the mask signal or a value indicating a logic high state as a switching control signal for a cutoff switch under the control of a LOCK signal; the cutoff switch configured to control transmission of the input signal (the CED signal) to the delay line in response to the mask signal or the control signal indicating the logic high state applied from the pass switch, and detect the rising edge or the falling edge of the input signal; and a pull-up section and a pull-down section configured to complementarily operate by at least one signal of the delayed clock signals when the cutoff switch is turned off by the mask signal, and output the master clock signal to the delay line.
 5. The receiver according to claim 4, wherein the pass switch perceives a logic low state of the LOCK signal as the clock training interval and applies the value indicating the logic high state as the control signal for the cutoff switch; and wherein the cutoff switch outputs the input signal (the CED signal) as it is, as the master clock signal in response to the value indicating the logic high state transmitted from the pass switch and transmits the input signal (the CED signal) to the delay line.
 6. The receiver according to claim 4, wherein the pass switch applies the mask signal as the control signal for the cutoff switch when the LOCK signal is in the logic high state; and wherein the cutoff switch detects the rising edge or the falling edge of the input signal (the CED signal) during an interval in which the mask signal is in the logic high state and outputs a detection result to the delay line, prevents the input signal (the CED signal) from being transferred as it is when the mask signal is in a logic low state, and operates the pull-up section or the pull-down section using the at least one delayed clock signal and recovers and transmits a remaining portion of the input signal (the CED signal) excluding the rising edge or the falling edge of the clock signal.
 7. The receiver according to claim 3, wherein, in order to generate the delayed clock signals having a number equal to or greater than 2N+1 (N is a natural number indicating a number of data bits that exist in the input signal (the CED signal)), the delay line is provided with the delay means which have a number corresponding to the number of the delayed clock signals.
 8. The receiver according to claim 3, wherein the delay line comprises a voltage-controlled delay line or a current-controlled delay line.
 9. The receiver according to claim 3, wherein the delay means comprise inverters.
 10. The receiver according to claim 3, wherein the phase difference detector is configured to have, as its inputs being comparison targets, two optional clock signals among the master clock signal outputted from the clock generator and the delayed clock signals outputted from the delay line when the LOCK signal is in the logic high state and the delay locked loop is locked, and generate the up/down signal as a delay amount control signal.
 11. The receiver according to claim 3, wherein the low pass filter comprises a charge pump which has an output terminal connected to the delay line. 